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Serial peripheral interface (SPI)
RM0008
LSB justified standard
This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit
full-accuracy frame formats).
Figure 221. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0
CK
WS
Transmission
Reception
SD
MSB
May be 16-bit, 32-bit
LSB MSB
Channel left
Channel right
Figure 222. LSB Justified 24-bit frame length with CPOL = 0
CK
WS
Transmission
Reception
SD
8-bit data
0 forced
MSB
24-bit remaining
LSB
Channel left 32-bit
Channel right
●
In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register
are required from software or by DMA. The operations are shown below.
Figure 223. Operations required to transmit 0x3478AE
First write to Data register
conditioned by TXE = ‘1’
0xXX34
Only the 8 LSB bits of the half-word
are significant. Whatever the 8 MSBs
a field of 0x00 is forced instead
Second write to Data register
conditioned by TXE = ‘1’
0x78AE
604/995
●
In reception mode:
If data 0x3478AE are received, two successive read operations from SPI_DR are
required on each RXNE event.
Doc ID 13902 Rev 9
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